Aufgaben:Exercise 1.6: Cyclic Redundancy Check: Difference between revisions

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Die Anzapfungen des Schieberegisters sind  $g_{0} = 1, \ g_{1} = 1, \ g_{2} = 0, \ g_{3} = 0$  und  $g_{4} = 1$.  
The taps of the shift register are  $g_{0} = 1, \ g_{1} = 1, \ g_{2} = 0, \ g_{3} = 0$  and  $g_{4} = 1$.  
*Das dazugehörige Generatorpolynom lautet:
*The corresponding generator polynomial is:
:$$G(D) = D^4 + D +1 \hspace{0.05cm}.$$
:$$G(D) = D^4 + D +1 \hspace{0.05cm}.$$
*Die sendeseitige CRC4–Prüfsumme erhält man auch als  '''Rest'''  der Polynomdivision
*The CRC4 checksum on the transmission side is also obtained as the  '''remainder'''  of the polynomial division
:$$(D^{11} +D^{9} +D^{8}+D^{6}+D^{5})/G(D) \hspace{0.05cm}.$$
:$$(D^{11} +D^{9} +D^{8}+D^{6}+D^{5})/G(D) \hspace{0.05cm}.$$
*Das Divisorpolynom ergibt sich aus der Eingangsfolge und vier angehängten Nullen:  $\rm 1011\hspace{0.09cm} 0110\hspace{0.09cm} 0000$.
*The divisor polynomial results from the input sequence and four appended zeros:  $\rm 1011\hspace{0.09cm} 0110\hspace{0.09cm} 0000$.




Auch die CRC4–Überprüfung beim Empfänger entsprechend Teilaufgabe  '''(4)'''  kann durch eine Polynomdivision dargestellt werden. Sie lässt sich durch eine Schieberegisterstruktur in ähnlicher Weise realisieren wie die sendeseitige Gewinnung der CRC4–Prüfsumme.
The CRC4 check at the receiver according to subtask  '''(4)'''  can also be represented by a polynomial division. It can be implemented by a shift register structure in a similar way as the CRC4 checksum is obtained at the transmitting end.




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''Hinweise:''  
''Notes:''  


*Die Aufgabe gehört zum Kapitel  [[Examples_of_Communication_Systems/ISDN_Primary_Multiplex_Connection|"ISDN Primary Multiplex Connection"]] .  
*The exercise belongs to the chapter  [[Examples_of_Communication_Systems/ISDN_Primary_Multiplex_Connection|"ISDN Primary Multiplex Connection"]] .  
*Zur Lösung der Aufgabe werden einige Grundkenntnisse der  [[Channel_Coding|Kanalcodierung]]  vorausgesetzt.
*To solve the exercise, some basic knowledge of  [[Channel_Coding|"channel coding]]  is required.
   
   






===Fragebogen===
===Questions===


<quiz display=simple>
<quiz display=simple>


{Welches Ergebnis&nbsp; $E(D)$&nbsp; und welchen Rest&nbsp; $R(D)$&nbsp; liefert die Polynomdivision
{Which result&nbsp; $E(D)$&nbsp; and which remainder&nbsp; $R(D)$&nbsp; results from the polynomial division
$(D^{11} + D^{9} + D^{8} + D^{6} + D^{5}) : (D^{4} + D + 1)$&nbsp;?
$(D^{11} + D^{9} + D^{8} + D^{6} + D^{5}) : (D^{4} + D + 1)$&nbsp;?
|type="()"}
|type="()"}
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- $E(D) = D^{7} + D^{5} + D^{3} + 1, \hspace{1cm}R(D) = 0$.
- $E(D) = D^{7} + D^{5} + D^{3} + 1, \hspace{1cm}R(D) = 0$.


{Wie lautet die CRC–Prüfsumme im vorliegenden Fall?
{What is the CRC checksum in the present case?
|type="{}"}
|type="{}"}
$\rm CRC0 \ = \ $ { 1 3% }  
$\rm CRC0 \ = \ $ { 1 3% }  
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$\rm CRC3 \ = \ $ { 1 3% }  
$\rm CRC3 \ = \ $ { 1 3% }  


{Am Empfänger kommen folgende Bitfolgen an, jeweils&nbsp; $\text{acht Informationsbits plus  (CRC3, CRC2, CRC1,CRC0)}$. <br>Wann liegt kein Bitfehler vor?
{The following bit sequences arrive at the receiver, &nbsp; $\text{eight information bits each plus  (CRC3, CRC2, CRC1,CRC0)}$. <br>When is there no bit error?
|type="[]"}
|type="[]"}
- $1011 \hspace{0.1cm}0010\hspace{0.08cm} 1011$,
- $1011 \hspace{0.1cm}0010\hspace{0.08cm} 1011$,
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- $1011 \hspace{0.1cm}0110\hspace{0.08cm} 1001$.
- $1011 \hspace{0.1cm}0110\hspace{0.08cm} 1001$.


{Welche empfangene Bitfolgen wurden bei der Übertragung verfälscht?
{Which received bit sequences were falsified during transmission?
|type="[]"}
|type="[]"}
+ $0000 \hspace{0.1cm}0111 \hspace{0.1cm}0010$,
+ $0000 \hspace{0.1cm}0111 \hspace{0.1cm}0010$,
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</quiz>
</quiz>


===Musterlösung===
===Solution===
{{ML-Kopf}}
{{ML-Kopf}}


'''(1)'''&nbsp; Richtig ist <u>der Lösungsvorschlag 2</u>:
'''(1)'''&nbsp; <u>Solution 2</u> is correct:
*Aufgrund des größten Zählerexponenten $(D^{11})$ und des höchsten Nennerexponenten $(D^{4})$ kann der erste Vorschlag $E(D) = D^{5} + D^{3} + 1$ als Ergebnis ausgeschlossen werden &nbsp; &rArr; &nbsp; $E(D) = D^{7} + D^{5} + D^{3} + 1$.  
*Due to the largest numerator exponent $(D^{11})$ and the highest denominator exponent $(D^{4})$, the first suggestion $E(D) = D^{5} + D^{3} + 1$ can be excluded as the result &nbsp; &rArr; &nbsp; $E(D) = D^{7} + D^{5} + D^{3} + 1$.  




*Die Modulo–2–Multiplikation von $E(D)$ mit dem Generatorpolynom $G(D) = D^{4} + D + 1$ liefert:
*Modulo-2 multiplication of $E(D)$ by the generator polynomial $G(D) = D^{4} + D + 1$ yields:
:$$E(D) \cdot G(D) \ = \ (D^7+ D^5+D^3+1)\cdot (D^4+ D+1) \ = D^{11}+D^8+D^7+D^9+D^6+D^5+D^7+D^4+D^3+D^4+ D+1 \hspace{0.05cm}.$$
:$$E(D) \cdot G(D) \ = \ (D^7+ D^5+D^3+1)\cdot (D^4+ D+1) \ = D^{11}+D^8+D^7+D^9+D^6+D^5+D^7+D^4+D^3+D^4+ D+1 \hspace{0.05cm}.$$
*Zu berücksichtigen ist hierbei, dass bei Modulo–2–Rechnungen $D^{4} + D^{4} = 0$ gilt. Damit ergibt sich der folgende Rest:
*It must be taken into account here that for modulo-2 calculations $D^{4} + D^{4} = 0$. This results in the following remainder:
:$$R(D) = D^{11}+D^9+D^8+D^6+D^5- E(D) \cdot G(D) = D^3+D+1 \hspace{0.05cm}.$$
:$$R(D) = D^{11}+D^9+D^8+D^6+D^5- E(D) \cdot G(D) = D^3+D+1 \hspace{0.05cm}.$$




  [[File:P_ID1628__Bei_A_1_6b.png|right|frame|Registerbelegungen bei CRC4]]
  [[File:P_ID1628__Bei_A_1_6b.png|right|frame|Register assignments for CRC4]]
'''(2)'''&nbsp; Aus dem Ergebnis der Teilaufgabe '''(1)''' folgt:
'''(2)'''&nbsp; From the result of subtask '''(1)''' follows:
:$${\rm CRC0 = 1},\hspace{0.2cm}{\rm CRC1 = 1},\hspace{0.2cm}{\rm CRC2 = 0},\hspace{0.2cm}{\rm CRC3 = 1}\hspace{0.05cm}.$$
:$${\rm CRC0 = 1},\hspace{0.2cm}{\rm CRC1 = 1},\hspace{0.2cm}{\rm CRC2 = 0},\hspace{0.2cm}{\rm CRC3 = 1}\hspace{0.05cm}.$$
Die Tabelle zeigt einen zweiten Lösungsweg auf: Sie enthält die Registerbelegungen der gegebenen Schaltung zu den Zeiten 0, ... , 8.
The table shows a second way of solution: It contains the register assignments of the given circuit at the times 0, ... , 8.
<br clear=all>
<br clear=all>
'''(3)'''&nbsp; Richtig ist nur der <u>Lösungsvorschlag 2</u>.:
'''(3)'''&nbsp; Only <u>solution 2</u> is correct:
*Der Empfänger teilt das Polynom $P(D)$ der Empfangsfolge durch das Generatorpolynom $G(D)$.  
*The receiver divides the polynomial $P(D)$ of the receive sequence by the generator polynomial $G(D)$.  
*Liefert diese Modulo–2–Division den Rest $R(D) = 0$, so wurden alle 12 Bit richtig übertragen.  
*If this modulo-2 division returns the remainder $R(D) = 0$, then all 12 bits were transmitted correctly.
*Dies trifft für den zweiten Lösungsvorschlag zu, wie ein Vergleich mit den Teilaufgaben (1) und (2) zeigt. Es gilt ohne Rest:
*This is true for the second solution, as a comparison with subtasks (1) and (2) shows. It is valid without remainder:
:$$(D^{11}+D^9+D^8+D^6+D^5+D^3+D+1) : (D^4+ D+1)= D^7+D^5+D^3+1 \hspace{0.05cm}.$$
:$$(D^{11}+D^9+D^8+D^6+D^5+D^3+D+1) : (D^4+ D+1)= D^7+D^5+D^3+1 \hspace{0.05cm}.$$
*Bei Lösungsvorschlag 1 wurde das 6. Informationsbit verfälscht, beim Lösungsvorschlag 3 das CRC1–Bit.  
*In solution 1 the 6th information bit was corrupted, in solution 3 the CRC1 bit.




'''(4)'''&nbsp; Richtig sind  <u>die Lösungsvorschläge 1 und 3</u>:
'''(4)'''&nbsp; <u>Solutions 1 and 3</u> are correct:
*Die Grafik verdeutlicht die Modulo–2–Divisionen für die gegebenen Empfangsfolgen in vereinfachter Form (mit Nullen und Einsen).  
*The diagram illustrates the modulo-2 divisions for the given received sequences in simplified form (with zeros and ones).
*Man erkennt, dass nur bei der Folge 2 die Division ohne Rest möglich ist.  
*You can see that only for sequence 2 the division without remainder is possible.
*In ausgeschriebener Form lauten die Polynomdivisionen:
*In written form, the polynomial divisions are:
:$$\ (1) \ \hspace{0.2cm}(D^6+D^5+D^4+1) : (D^4+ D+1)\hspace{0.3cm}\Rightarrow \hspace{0.3cm}{\rm Rest}\hspace{0.15cm}D^3+ D+1\hspace{0.05cm},$$  
:$$\ (1) \ \hspace{0.2cm}(D^6+D^5+D^4+1) : (D^4+ D+1)\hspace{0.3cm}\Rightarrow \hspace{0.3cm}{\rm Rest}\hspace{0.15cm}D^3+ D+1\hspace{0.05cm},$$  
:$$\ (2) \ \hspace{0.2cm}(D^7+D^6+D^5+D^4+1) : (D^4+ D+1)\hspace{0.3cm}\Rightarrow \hspace{0.3cm}{\rm ohne \hspace{0.15cm}Rest}\hspace{0.05cm},$$  
:$$\ (2) \ \hspace{0.2cm}(D^7+D^6+D^5+D^4+1) : (D^4+ D+1)\hspace{0.3cm}\Rightarrow \hspace{0.3cm}{\rm ohne \hspace{0.15cm}Rest}\hspace{0.05cm},$$  
:$$\ (3) \ \hspace{0.2cm}(D^7+D^6+D^5+D^4+D^3+1) : (D^4+ D+1) \hspace{0.3cm}\Rightarrow \hspace{0.3cm}{\rm Rest}\hspace{0.15cm}D^3\hspace{0.05cm}.$$
:$$\ (3) \ \hspace{0.2cm}(D^7+D^6+D^5+D^4+D^3+1) : (D^4+ D+1) \hspace{0.3cm}\Rightarrow \hspace{0.3cm}{\rm Rest}\hspace{0.15cm}D^3\hspace{0.05cm}.$$
[[File:P_ID1629__Bei_A_1_6d.png|center|frame|Polynomdivision der drei Empfangsfolgen]]
[[File:P_ID1629__Bei_A_1_6d.png|center|frame|Polynomial division of the three received sequences]]


{{ML-Fuß}}
{{ML-Fuß}}

Revision as of 22:58, 25 October 2022


Formation of the CRC4 checksum

The synchronization happens at the primary multiplex connection in each case in channel  $0$  – the synchronization channel - of each frame:

  • For odd time frames  (number 1, 3, ... , 15)  this transmits the so-called "frame password" with the fixed bit pattern  $\rm X001\hspace{0.05cm} 1011$.
  • Each even frame  (with number 2, 4, ... , 16)  on the other hand contains the "message word"  $\rm X1DN\hspace{0.05cm}YYYY$.
  • Error messages are signaled via the  $\rm D$ bit and the   $\rm N$ bit, and the four  $\rm Y$ bits are reserved for service functions.


The  $\rm X$ bit is obtained in each case by the CRC4 method, the implementation of which is shown in the diagram:

  • From eight input bits each - in the entire exercise the bit sequence  $\rm 1011\hspace{0.05cm} 0110$ is assumed for this purpose - the four check bits  $\rm CRC3$, ... , $\rm CRC0$  are obtained by modulo-2 additions and shifts, which are added to the input word in this order.
  • Before the first bit is shifted into the register, all registers are filled with zeros:
$${\rm CRC3 = CRC2 =CRC1 =CRC0 = 0}\hspace{0.05cm}.$$
  • After eight shift clocks, the four registers  $\rm CRC3$, ... , $\rm CRC0$  contains the CRC4 checksum.


The taps of the shift register are  $g_{0} = 1, \ g_{1} = 1, \ g_{2} = 0, \ g_{3} = 0$  and  $g_{4} = 1$.

  • The corresponding generator polynomial is:
$$G(D) = D^4 + D +1 \hspace{0.05cm}.$$
  • The CRC4 checksum on the transmission side is also obtained as the  remainder  of the polynomial division
$$(D^{11} +D^{9} +D^{8}+D^{6}+D^{5})/G(D) \hspace{0.05cm}.$$
  • The divisor polynomial results from the input sequence and four appended zeros:  $\rm 1011\hspace{0.09cm} 0110\hspace{0.09cm} 0000$.


The CRC4 check at the receiver according to subtask  (4)  can also be represented by a polynomial division. It can be implemented by a shift register structure in a similar way as the CRC4 checksum is obtained at the transmitting end.




Notes:



Questions

1 Which result  $E(D)$  and which remainder  $R(D)$  results from the polynomial division $(D^{11} + D^{9} + D^{8} + D^{6} + D^{5}) : (D^{4} + D + 1)$ ?

$E(D) = D^{5} + D^{3} + 1, \hspace{2.13cm}R(D) = D^{3} + D$,
$E(D) = D^{7} + D^{5} + D^{3} + 1, \hspace{1cm}R(D) = D^{3} + D + 1$,
$E(D) = D^{7} + D^{5} + D^{3} + 1, \hspace{1cm}R(D) = 0$.

2 What is the CRC checksum in the present case?

$\rm CRC0 \ = \ $
$\rm CRC1 \ = \ $
$\rm CRC2 \ = \ $
$\rm CRC3 \ = \ $

3 The following bit sequences arrive at the receiver,   $\text{eight information bits each plus (CRC3, CRC2, CRC1,CRC0)}$.
When is there no bit error?

$1011 \hspace{0.1cm}0010\hspace{0.08cm} 1011$,
$1011 \hspace{0.1cm}0110 \hspace{0.08cm}1011$,
$1011 \hspace{0.1cm}0110\hspace{0.08cm} 1001$.

4 Which received bit sequences were falsified during transmission?

$0000 \hspace{0.1cm}0111 \hspace{0.1cm}0010$,
$0000 \hspace{0.1cm}1111\hspace{0.1cm} 0010$,
$0000\hspace{0.1cm} 1111\hspace{0.1cm} 1010$.


Solution

(1)  Solution 2 is correct:

  • Due to the largest numerator exponent $(D^{11})$ and the highest denominator exponent $(D^{4})$, the first suggestion $E(D) = D^{5} + D^{3} + 1$ can be excluded as the result   ⇒   $E(D) = D^{7} + D^{5} + D^{3} + 1$.


  • Modulo-2 multiplication of $E(D)$ by the generator polynomial $G(D) = D^{4} + D + 1$ yields:
$$E(D) \cdot G(D) \ = \ (D^7+ D^5+D^3+1)\cdot (D^4+ D+1) \ = D^{11}+D^8+D^7+D^9+D^6+D^5+D^7+D^4+D^3+D^4+ D+1 \hspace{0.05cm}.$$
  • It must be taken into account here that for modulo-2 calculations $D^{4} + D^{4} = 0$. This results in the following remainder:
$$R(D) = D^{11}+D^9+D^8+D^6+D^5- E(D) \cdot G(D) = D^3+D+1 \hspace{0.05cm}.$$


Register assignments for CRC4

(2)  From the result of subtask (1) follows:

$${\rm CRC0 = 1},\hspace{0.2cm}{\rm CRC1 = 1},\hspace{0.2cm}{\rm CRC2 = 0},\hspace{0.2cm}{\rm CRC3 = 1}\hspace{0.05cm}.$$

The table shows a second way of solution: It contains the register assignments of the given circuit at the times 0, ... , 8.
(3)  Only solution 2 is correct:

  • The receiver divides the polynomial $P(D)$ of the receive sequence by the generator polynomial $G(D)$.
  • If this modulo-2 division returns the remainder $R(D) = 0$, then all 12 bits were transmitted correctly.
  • This is true for the second solution, as a comparison with subtasks (1) and (2) shows. It is valid without remainder:
$$(D^{11}+D^9+D^8+D^6+D^5+D^3+D+1) : (D^4+ D+1)= D^7+D^5+D^3+1 \hspace{0.05cm}.$$
  • In solution 1 the 6th information bit was corrupted, in solution 3 the CRC1 bit.


(4)  Solutions 1 and 3 are correct:

  • The diagram illustrates the modulo-2 divisions for the given received sequences in simplified form (with zeros and ones).
  • You can see that only for sequence 2 the division without remainder is possible.
  • In written form, the polynomial divisions are:
$$\ (1) \ \hspace{0.2cm}(D^6+D^5+D^4+1) : (D^4+ D+1)\hspace{0.3cm}\Rightarrow \hspace{0.3cm}{\rm Rest}\hspace{0.15cm}D^3+ D+1\hspace{0.05cm},$$
$$\ (2) \ \hspace{0.2cm}(D^7+D^6+D^5+D^4+1) : (D^4+ D+1)\hspace{0.3cm}\Rightarrow \hspace{0.3cm}{\rm ohne \hspace{0.15cm}Rest}\hspace{0.05cm},$$
$$\ (3) \ \hspace{0.2cm}(D^7+D^6+D^5+D^4+D^3+1) : (D^4+ D+1) \hspace{0.3cm}\Rightarrow \hspace{0.3cm}{\rm Rest}\hspace{0.15cm}D^3\hspace{0.05cm}.$$
Polynomial division of the three received sequences