Difference between revisions of "Aufgaben:Exercise 1.6: Cyclic Redundancy Check"

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{{quiz-Header|Buchseite=Beispiele von Nachrichtensystemen/ISDN–Primärmultiplexanschluss
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{{quiz-Header|Buchseite=Examples_of_Communication_Systems/ISDN_Primary_Multiplex_Connection
  
 
}}
 
}}
  
[[File:P_ID1626__Bei_A_1_6.png|right|frame|Bildung der CRC4-Prüfsumme]]
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[[File:P_ID1626__Bei_A_1_6.png|right|frame|CRC4 checksum formation]]
Die Synchronisation geschieht beim Primärmultiplexanschluss jeweils im Kanal $0$ – dem Synchronisationskanal – eines jeden Rahmens:
+
The synchronization happens at the primary multiplex connection in each case in synchronization channel  "$0$"   of each frame:
* Bei ungeraden Zeitrahmen (Nummer 1, 3, ... , 15) überträgt dieser das so genannte „Rahmenkennwort” mit dem festen Bitmuster '''X001 1011'''.
+
# For odd time frames  (number 1, 3, ... , 15)  this transmits the so-called  "frame password"  with the fixed bit pattern  $\rm X001\hspace{0.05cm} 1011$.
* Jeder gerade Rahmen (mit Nummer 2, 4, ... , 16) beinhaltet dagegen das „Meldewort” '''X1DN YYYY'''.  
+
# Each even frame  (with number 2, 4, ... , 16)  on the other hand contains the  "message word"  $\rm X1DN\hspace{0.05cm}YYYY$.
*Über das D–Bit und das N–Bit werden Fehlermeldungen signalisiert und die vier Y–Bits sind für Service–Funktionen reserviert.
+
# Error messages are signaled via the  $\rm D$  bit and the   $\rm N$  bit.  The four  $\rm Y$  bits are reserved for service functions.
  
  
Das X–Bit wird jeweils durch das ''CRC4''–Verfahren gewonnen, dessen Realisierung in der Grafik dargestellt ist:  
+
The  $\rm X$  bit is obtained in each case by the  "CRC4 method",  the implementation of which is shown in the diagram:
*Aus jeweils acht Eingangsbits – in der gesamten Aufgabe wird hierfür die Bitfolge '''1011 0110''' angenommen – werden durch Modulo–2–Additionen und Verschiebungen die vier Prüfbits $\rm CRC3$, ... , $\rm CRC0$ gewonnen, die dem Eingangswort in dieser Reihenfolge hinzugefügt werden.
+
*From eight input bits each - in the entire exercise the bit sequence  "$\rm 1011\hspace{0.05cm} 0110$"  is assumed for this purpose - the four check bits  $\rm CRC3$, ... , $\rm CRC0$  are obtained by modulo-2 additions and shifts,  which are added to the input word in this order.
*Bevor das erste Bit in das Register geschoben wird, sind alle Register mit Nullen belegt:
+
 
 +
*Before the first bit is shifted into the register,  all registers are filled with zeros:
 
:$${\rm CRC3 = CRC2 =CRC1 =CRC0 = 0}\hspace{0.05cm}.$$
 
:$${\rm CRC3 = CRC2 =CRC1 =CRC0 = 0}\hspace{0.05cm}.$$
*Nach 8 Schiebetakten steht in den vier Registern $\rm CRC3$, ... , $\rm CRC0$ die CRC4–Prüfsumme.
+
*After eight shift clocks,  the four registers  $\rm CRC3$, ... , $\rm CRC0$  contains the CRC4 checksum.
 +
 
  
  
Die Anzapfungen des Schieberegisters sind $g_{0} = 1, g_{1} = 1, g_{2} = 0, g_{3} = 0$ und $g_{4} = 1$.  
+
The taps of the shift register are  $g_{0} = 1, \ g_{1} = 1, \ g_{2} = 0, \ g_{3} = 0$  and  $g_{4} = 1$.  
*Das dazugehörige Generatorpolynom lautet:
+
*The corresponding generator polynomial is:
 
:$$G(D) = D^4 + D +1 \hspace{0.05cm}.$$
 
:$$G(D) = D^4 + D +1 \hspace{0.05cm}.$$
*Die sendeseitige CRC4–Prüfsumme erhält man auch als '''Rest''' der Polynomdivision
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*The CRC4 checksum on the transmission side is also obtained as the   "'''remainder'''"   of the polynomial division
 
:$$(D^{11} +D^{9} +D^{8}+D^{6}+D^{5})/G(D) \hspace{0.05cm}.$$
 
:$$(D^{11} +D^{9} +D^{8}+D^{6}+D^{5})/G(D) \hspace{0.05cm}.$$
*Das Divisorpolynom ergibt sich aus der Eingangsfolge und vier angehängten Nullen: '''1011 0110 0000'''.
+
*The divisor polynomial results from the input sequence and four appended zeros:  "$\rm 1011\hspace{0.09cm} 0110\hspace{0.09cm} 0000$".
 +
 
  
 +
The CRC4 check at the receiver according to subtask  '''(4)'''  can also be represented by a polynomial division.  It can be implemented by a shift register structure in a similar way as the CRC4 checksum is obtained at the transmitting end.
  
Auch die CRC4–Überprüfung beim Empfänger entsprechend Teilaufgabe (4) kann durch eine Polynomdivision dargestellt werden. Sie lässt sich durch eine Schieberegisterstruktur in ähnlicher Weise realisieren wie die sendeseitige Gewinnung der CRC4–Prüfsumme.
 
  
  
  
  
''Hinweise:''
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Notes:  
  
*Die Aufgabe gehört zum Kapitel [[Beispiele_von_Nachrichtensystemen/ISDN–Primärmultiplexanschluss|ISDN–Primärmultiplexanschluss]] .  
+
*The exercise belongs to the chapter  [[Examples_of_Communication_Systems/ISDN_Primary_Multiplex_Connection|"ISDN Primary Multiplex Connection"]] .  
*Zur Lösung der Aufgabe werden einige Grundkenntnisse der [[Kanalcodierung|Kanalcodierung]] vorausgesetzt.
+
*To solve the exercise, some basic knowledge of  [[Channel_Coding|"Channel Coding"]]  is required.
*Sollte die Eingabe des Zahlenwertes „0” erforderlich sein, so geben Sie bitte „0.” ein.
+
  
  
  
===Fragebogen===
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===Questions===
  
 
<quiz display=simple>
 
<quiz display=simple>
  
{Welches Ergebnis E und welchen Rest R liefert die Polynomdivision
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{Which result&nbsp; $E(D)$&nbsp; and which remainder&nbsp; $R(D)$&nbsp; results from the polynomial division
$(D^{11} + D^{9} + D^{8} + D^{6} + D^{5}) : (D^{4} + D + 1)?
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$(D^{11} + D^{9} + D^{8} + D^{6} + D^{5}) : (D^{4} + D + 1)$&nbsp;?
|type="[]"}
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|type="()"}
- $E(D) = D^{5} + D^{3} + 1, R(D) = D^{3} + D$,
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- $E(D) = D^{5} + D^{3} + 1, \hspace{2.13cm}R(D) = D^{3} + D$,
+ $E(D) = D^{7} + D^{5} + D^{3} + 1, R(D) = D^{3} + D + 1$,
+
+ $E(D) = D^{7} + D^{5} + D^{3} + 1, \hspace{1cm}R(D) = D^{3} + D + 1$,
- $E(D) = D^{7} + D^{5} + D^{3} + 1, R(D) = 0$.
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- $E(D) = D^{7} + D^{5} + D^{3} + 1, \hspace{1cm}R(D) = 0$.
  
{Wie lautet die CRC–Prüfsumme?
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{What is the CRC checksum in the present case?
 
|type="{}"}
 
|type="{}"}
$CRC0 \ = \ $ { 1 3% }  
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$\rm CRC0 \ = \ $ { 1 3% }  
$CRC1 \ = \ $ { 1 3% }  
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$\rm CRC1 \ = \ $ { 1 3% }  
$CRC2 \ = \ $ { 0 3% }  
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$\rm CRC2 \ = \ $ { 0. }  
$CRC3 \ = \ $ { 1 3% }  
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$\rm CRC3 \ = \ $ { 1 3% }  
  
{Am Empfänger kommen folgende Bitfolgen an, jeweils 8 Informationsbits + (CRC3, CRC2, CRC1,CRC0). Wann liegt kein Bitfehler vor?
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{The following bit sequences arrive at the receiver,&nbsp; eight information bits each plus&nbsp; $\text{  (CRC3, CRC2, CRC1,CRC0)}$.&nbsp; <br>What bit sequences indicate that there is no bit error?
 
|type="[]"}
 
|type="[]"}
- '''1011 0010 1011''',
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- $1011 \hspace{0.1cm}0010\hspace{0.08cm} 1011$,
+ '''1011 0110 1011''',  
+
+ $1011 \hspace{0.1cm}0110 \hspace{0.08cm}1011$,  
- '''1011 0110 1001'''.
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- $1011 \hspace{0.1cm}0110\hspace{0.08cm} 1001$.
  
{Welche empfangene Bitfolgen wurden bei der Übertragung verfälscht?
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{Which of the following received bit sequences were falsified during transmission?
 
|type="[]"}
 
|type="[]"}
+ '''0000 0111 0010''',
+
+ $0000 \hspace{0.1cm}0111 \hspace{0.1cm}0010$,
- '''0000 1111 0010''',  
+
- $0000 \hspace{0.1cm}1111\hspace{0.1cm} 0010$,  
+ '''0000 1111 1010'''.
+
+ $0000\hspace{0.1cm} 1111\hspace{0.1cm} 1010$.
  
 
</quiz>
 
</quiz>
  
===Musterlösung===
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===Solution===
 
{{ML-Kopf}}
 
{{ML-Kopf}}
  
'''(1)'''&nbsp; Aufgrund des größten Zählerexponenten ($D^{11}$) und des höchsten Nennerexponenten ($D^{4}$) kann der Vorschlag $E(D) = D^{5} + D^{3} + 1$ als Ergebnis ausgeschlossen werden $\Rightarrow E(D) = D^{7} + D^{5} + D^{3} + 1$. Die Modulo–2–Multiplikation von $E(D)$ mit dem Generatorpolynom $G(D) = D^{4} + D + 1$ liefert:
+
'''(1)'''&nbsp; The&nbsp; <u>Solution 2</u>&nbsp; is correct:
:$$E(D) \cdot G(D) \ = \ (D^7+ D^5+D^3+1)\cdot (D^4+ D+1) \ = \ $$
+
*Due to the largest numerator exponent&nbsp; $(D^{11})$&nbsp; and the highest denominator exponent&nbsp; $(D^{4})$,&nbsp; the first suggestion&nbsp; $E(D) = D^{5} + D^{3} + 1$&nbsp; can be excluded as the result &nbsp; &rArr; &nbsp; $E(D) = D^{7} + D^{5} + D^{3} + 1$.  
:$$\hspace{2.2cm} \ = \ D^{11}+D^8+D^7+D^9+D^6+D^5+$$
+
 
:$$\hspace{2.2cm} \ + \ D^7+D^4+D^3+D^4+ D+1 \hspace{0.05cm}.$$
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*Modulo-2 multiplication of&nbsp; $E(D)$&nbsp; by the generator polynomial&nbsp; $G(D) = D^{4} + D + 1$&nbsp; yields:
Zu berücksichtigen ist hierbei, dass bei Modulo–2–Rechnungen $D^{4} + D^{4} = 0$ gilt. Damit ergibt sich der folgende Rest:
+
:$$E(D) \cdot G(D) \ = \ (D^7+ D^5+D^3+1)\cdot (D^4+ D+1) \ = D^{11}+D^8+D^7+D^9+D^6+D^5+D^7+D^4+D^3+D^4+ D+1 \hspace{0.05cm}.$$
 +
*It must be taken into account here that for modulo-2 calculations $D^{4} + D^{4} = 0$. This results in the following remainder:
 
:$$R(D) = D^{11}+D^9+D^8+D^6+D^5- E(D) \cdot G(D) = D^3+D+1 \hspace{0.05cm}.$$
 
:$$R(D) = D^{11}+D^9+D^8+D^6+D^5- E(D) \cdot G(D) = D^3+D+1 \hspace{0.05cm}.$$
Richtig ist somit <u>der Lösungsvorschlag 2</u>.
 
  
'''(2)'''&nbsp; [[File:P_ID1628__Bei_A_1_6b.png|right|frame|Registerbelegungen bei CRC4]]
 
Aus dem Ergebnis der Aufgabe (1) folgt:
 
:$${\rm CRC0 = 1},\hspace{0.2cm}{\rm CRC1 = 1},$$
 
:$$\hspace{0.2cm}{\rm CRC2 = 0},\hspace{0.2cm}{\rm CRC3 = 1}\hspace{0.05cm}.$$
 
Die Tabelle zeigt einen zweiten Lösungsweg auf: Sie enthält die Registerbelegungen der gegebenen Schaltung zu den Taktzeiten 0, ... , 8.
 
  
'''(3)'''&nbsp; Der Empfänger teilt das Polynom $P(D)$ der Empfangsfolge durch das Generatorpolynom $G(D)$. Liefert diese Modulo–2–Division den Rest $R(D) = 0$, so wurden alle $12 \ \rm Bit$ richtig übertragen. Dies trifft für den zweiten Lösungsvorschlag zu, wie ein Vergleich mit den Aufgaben (1) und (2) zeigt. Es gilt ohne Rest:
+
[[File:EN_Bei_A_1_6b_ML.png|right|frame|Register assignments for CRC4]]
 +
'''(2)'''&nbsp; From the result of subtask&nbsp; '''(1)'''&nbsp; follows:
 +
:$${\rm CRC0 = 1},\hspace{0.2cm}{\rm CRC1 = 1},\hspace{0.2cm}{\rm CRC2 = 0},\hspace{0.2cm}{\rm CRC3 = 1}\hspace{0.05cm}.$$
 +
*The table shows a second way of solution:&nbsp;
 +
 
 +
*It contains the register assignments of the given circuit at times&nbsp; $0$, ... , $8$.
 +
 
 +
 
 +
 
 +
'''(3)'''&nbsp; Only&nbsp; <u>solution 2</u>&nbsp; is correct:
 +
*The receiver divides the polynomial&nbsp; $P(D)$&nbsp; of the received sequence by the generator polynomial&nbsp; $G(D)$.
 +
 +
*If this modulo-2 division returns the remainder&nbsp; $R(D) = 0$,&nbsp; then all&nbsp; $12$&nbsp; bits were transmitted correctly.
 +
 
 +
*This is true for the second solution,&nbsp; as a comparison with subtasks&nbsp; '''(1)'''&nbsp; and&nbsp; '''(2)'''&nbsp; shows.&nbsp; It is valid without remainder:
 
:$$(D^{11}+D^9+D^8+D^6+D^5+D^3+D+1) : (D^4+ D+1)= D^7+D^5+D^3+1 \hspace{0.05cm}.$$
 
:$$(D^{11}+D^9+D^8+D^6+D^5+D^3+D+1) : (D^4+ D+1)= D^7+D^5+D^3+1 \hspace{0.05cm}.$$
Bei Lösungsvorschlag 1 wurde das 6. Informationsbit verfälscht, beim letzten das CRC1–Bit. Richtig ist somit nur der <u>Lösungsvorschlag 2</u>.
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*In solution 1 the 6th information bit was falsified,&nbsp; in solution 3 the CRC1 bit.
 +
 
 +
 
 +
 
 +
'''(4)'''&nbsp; <u>Solutions 1 and 3</u> are correct:
 +
[[File:EN_Bei_A_1_6d.png|right|frame|Polynomial division of the three received sequences]]
 +
 
 +
*The diagram illustrates the modulo-2 divisions for the given received sequences in simplified form&nbsp; (with zeros and ones).
  
 +
*You can see that only for sequence 2 the division  is possible without remainder.
  
'''(4)'''&nbsp; Die folgende Grafik verdeutlicht die Modulo–2–Divisionen für die drei angegebenen Empfangsfolgen in vereinfachter Form (mit Nullen und Einsen). Man erkennt, dass nur bei der Folge 2 die Division ohne Rest möglich ist. Richtig sind also <u>die Lösungsvorschläge 1 und 3</u>.
+
*In written form, is possible the polynomial divisions are:
[[File:P_ID1629__Bei_A_1_6d.png|center|frame|Polynomdivision der drei Empfangsfolgen]]
+
$$\ (1) \ \hspace{0.2cm}(D^6+D^5+D^4+1) : (D^4+ D+1)$$
In ausgeschriebener Form lauten die Polynomdivisionen:
+
:$$\hspace{0.3cm}\Rightarrow \hspace{0.3cm}\text{remainder:}\hspace{0.15cm}D^3+ D+1\hspace{0.05cm},$$  
:$$\ (1) \ \hspace{0.2cm}(D^6+D^5+D^4+1) : (D^4+ D+1)\hspace{0.3cm}\Rightarrow \hspace{0.3cm}{\rm Rest}\hspace{0.15cm}D^3+ D+1\hspace{0.05cm},$$  
+
$$\ (2) \ \hspace{0.2cm}(D^7+D^6+D^5+D^4+1) : (D^4+ D+1)$$
:$$\ (2) \ \hspace{0.2cm}(D^7+D^6+D^5+D^4+1) : (D^4+ D+1)\hspace{0.3cm}\Rightarrow \hspace{0.3cm}{\rm ohne \hspace{0.15cm}Rest}\hspace{0.05cm},$$  
+
:$$\hspace{0.3cm}\Rightarrow \hspace{0.3cm}\text{remainder:}\hspace{0.15cm}0\hspace{0.05cm},$$  
:$$\ (3) \ \hspace{0.2cm}(D^7+D^6+D^5+D^4+D^3+1) : (D^4+ D+1) \hspace{0.3cm}\Rightarrow \hspace{0.3cm}{\rm Rest}\hspace{0.15cm}D^3\hspace{0.05cm}.$$
+
$$\ (3) \ \hspace{0.2cm}(D^7+D^6+D^5+D^4+D^3+1) : (D^4+ D+1)$$
 +
:$$\hspace{0.3cm}\Rightarrow \hspace{0.3cm}\text{remainder:}\hspace{0.15cm}D^3\hspace{0.05cm}.$$  
  
 
{{ML-Fuß}}
 
{{ML-Fuß}}
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[[Category:Aufgaben zu Beispiele von Nachrichtensystemen|^1.3 ISDN–Primärmultiplexanschluss
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[[Category:Examples of Communication Systems: Exercises|^1.3 ISDN Primary Multiplex Line^]]
^]]
 

Latest revision as of 17:31, 23 January 2023


CRC4 checksum formation

The synchronization happens at the primary multiplex connection in each case in synchronization channel  "$0$"  of each frame:

  1. For odd time frames  (number 1, 3, ... , 15)  this transmits the so-called  "frame password"  with the fixed bit pattern  $\rm X001\hspace{0.05cm} 1011$.
  2. Each even frame  (with number 2, 4, ... , 16)  on the other hand contains the  "message word"  $\rm X1DN\hspace{0.05cm}YYYY$.
  3. Error messages are signaled via the  $\rm D$  bit and the   $\rm N$  bit.  The four  $\rm Y$  bits are reserved for service functions.


The  $\rm X$  bit is obtained in each case by the  "CRC4 method",  the implementation of which is shown in the diagram:

  • From eight input bits each - in the entire exercise the bit sequence  "$\rm 1011\hspace{0.05cm} 0110$"  is assumed for this purpose - the four check bits  $\rm CRC3$, ... , $\rm CRC0$  are obtained by modulo-2 additions and shifts,  which are added to the input word in this order.
  • Before the first bit is shifted into the register,  all registers are filled with zeros:
$${\rm CRC3 = CRC2 =CRC1 =CRC0 = 0}\hspace{0.05cm}.$$
  • After eight shift clocks,  the four registers  $\rm CRC3$, ... , $\rm CRC0$  contains the CRC4 checksum.


The taps of the shift register are  $g_{0} = 1, \ g_{1} = 1, \ g_{2} = 0, \ g_{3} = 0$  and  $g_{4} = 1$.

  • The corresponding generator polynomial is:
$$G(D) = D^4 + D +1 \hspace{0.05cm}.$$
  • The CRC4 checksum on the transmission side is also obtained as the   "remainder"   of the polynomial division
$$(D^{11} +D^{9} +D^{8}+D^{6}+D^{5})/G(D) \hspace{0.05cm}.$$
  • The divisor polynomial results from the input sequence and four appended zeros:  "$\rm 1011\hspace{0.09cm} 0110\hspace{0.09cm} 0000$".


The CRC4 check at the receiver according to subtask  (4)  can also be represented by a polynomial division.  It can be implemented by a shift register structure in a similar way as the CRC4 checksum is obtained at the transmitting end.



Notes:



Questions

1

Which result  $E(D)$  and which remainder  $R(D)$  results from the polynomial division $(D^{11} + D^{9} + D^{8} + D^{6} + D^{5}) : (D^{4} + D + 1)$ ?

$E(D) = D^{5} + D^{3} + 1, \hspace{2.13cm}R(D) = D^{3} + D$,
$E(D) = D^{7} + D^{5} + D^{3} + 1, \hspace{1cm}R(D) = D^{3} + D + 1$,
$E(D) = D^{7} + D^{5} + D^{3} + 1, \hspace{1cm}R(D) = 0$.

2

What is the CRC checksum in the present case?

$\rm CRC0 \ = \ $

$\rm CRC1 \ = \ $

$\rm CRC2 \ = \ $

$\rm CRC3 \ = \ $

3

The following bit sequences arrive at the receiver,  eight information bits each plus  $\text{ (CRC3, CRC2, CRC1,CRC0)}$. 
What bit sequences indicate that there is no bit error?

$1011 \hspace{0.1cm}0010\hspace{0.08cm} 1011$,
$1011 \hspace{0.1cm}0110 \hspace{0.08cm}1011$,
$1011 \hspace{0.1cm}0110\hspace{0.08cm} 1001$.

4

Which of the following received bit sequences were falsified during transmission?

$0000 \hspace{0.1cm}0111 \hspace{0.1cm}0010$,
$0000 \hspace{0.1cm}1111\hspace{0.1cm} 0010$,
$0000\hspace{0.1cm} 1111\hspace{0.1cm} 1010$.


Solution

(1)  The  Solution 2  is correct:

  • Due to the largest numerator exponent  $(D^{11})$  and the highest denominator exponent  $(D^{4})$,  the first suggestion  $E(D) = D^{5} + D^{3} + 1$  can be excluded as the result   ⇒   $E(D) = D^{7} + D^{5} + D^{3} + 1$.
  • Modulo-2 multiplication of  $E(D)$  by the generator polynomial  $G(D) = D^{4} + D + 1$  yields:
$$E(D) \cdot G(D) \ = \ (D^7+ D^5+D^3+1)\cdot (D^4+ D+1) \ = D^{11}+D^8+D^7+D^9+D^6+D^5+D^7+D^4+D^3+D^4+ D+1 \hspace{0.05cm}.$$
  • It must be taken into account here that for modulo-2 calculations $D^{4} + D^{4} = 0$. This results in the following remainder:
$$R(D) = D^{11}+D^9+D^8+D^6+D^5- E(D) \cdot G(D) = D^3+D+1 \hspace{0.05cm}.$$


Register assignments for CRC4

(2)  From the result of subtask  (1)  follows:

$${\rm CRC0 = 1},\hspace{0.2cm}{\rm CRC1 = 1},\hspace{0.2cm}{\rm CRC2 = 0},\hspace{0.2cm}{\rm CRC3 = 1}\hspace{0.05cm}.$$
  • The table shows a second way of solution: 
  • It contains the register assignments of the given circuit at times  $0$, ... , $8$.


(3)  Only  solution 2  is correct:

  • The receiver divides the polynomial  $P(D)$  of the received sequence by the generator polynomial  $G(D)$.
  • If this modulo-2 division returns the remainder  $R(D) = 0$,  then all  $12$  bits were transmitted correctly.
  • This is true for the second solution,  as a comparison with subtasks  (1)  and  (2)  shows.  It is valid without remainder:
$$(D^{11}+D^9+D^8+D^6+D^5+D^3+D+1) : (D^4+ D+1)= D^7+D^5+D^3+1 \hspace{0.05cm}.$$
  • In solution 1 the 6th information bit was falsified,  in solution 3 the CRC1 bit.


(4)  Solutions 1 and 3 are correct:

Polynomial division of the three received sequences
  • The diagram illustrates the modulo-2 divisions for the given received sequences in simplified form  (with zeros and ones).
  • You can see that only for sequence 2 the division is possible without remainder.
  • In written form, is possible the polynomial divisions are:

$$\ (1) \ \hspace{0.2cm}(D^6+D^5+D^4+1) : (D^4+ D+1)$$

$$\hspace{0.3cm}\Rightarrow \hspace{0.3cm}\text{remainder:}\hspace{0.15cm}D^3+ D+1\hspace{0.05cm},$$

$$\ (2) \ \hspace{0.2cm}(D^7+D^6+D^5+D^4+1) : (D^4+ D+1)$$

$$\hspace{0.3cm}\Rightarrow \hspace{0.3cm}\text{remainder:}\hspace{0.15cm}0\hspace{0.05cm},$$

$$\ (3) \ \hspace{0.2cm}(D^7+D^6+D^5+D^4+D^3+1) : (D^4+ D+1)$$

$$\hspace{0.3cm}\Rightarrow \hspace{0.3cm}\text{remainder:}\hspace{0.15cm}D^3\hspace{0.05cm}.$$