Exercise 2.5: DSL Error Protection

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$\rm ADSL$ error protection

In order to decisively reduce the bit error rate of  $\rm xDSL$ systems, various backup procedures have been proposed in the specifications to counteract the two most common causes of errors:

• Bit errors due to impulse and crosstalk interference on the (two-wire) line,
• clipping of signal peaks due to lack of dynamic range of the transmit amplifiers (clipping).

The diagram shows the error protection measures for $\rm ADSL/DMT$. These are implemented in two different paths:

• In the  fast-path  one relies on lower waiting times.
• In the  interleaved-Path  a lower bit error rate is expected.

The assignment of the bits to these paths is done by a multiplexer $\rm (MUX)$ with synchronization control.

Hint:

• This exercise belongs to the chapter  "Methods to Reduce the Bit Error Rate in DSL".

Questions

1

Which statements are true for the two paths?

	The  interleaved-path  has greater latency.
	The  fast-Path  is more susceptible to AWGN noise.
	The  fast-Path  is more susceptible to bundle errors.

2

What are the tasks of the  cyclic redundancy check  (CRC) and the  Scrambler?

	CRC forms a parity-check value with $8$ bits from data blocks.
	The redundancy of the CRC is very high.
	The scrambler should avoid long zero sequences and one sequences.
	CRC and (de)scrambler are implemented with shift registers.

3

Which statements are true regarding forward error correction?

	DSL/DMT uses convolutional coding.
	DSL/DMT uses Reed-Solomon coding.
	The coding is done on byte level.
	It is a symbol-wise coding.

4

What are the tasks performed by  interleaving  and  de-interleaving?

	Improved correction capabilities for "Reed-Solomon".
	Interleaver and de-interleaver work on byte level.
	Interleaving adds redundancy.
	Interleaving is particularly suitable for real-time applications.

5

What are the tasks of the blocks  "Tone Ordering"  and "Gain Scaling"?

	Measurement of the channel characteristics of each bin.
	Allocation of the individual QAM signals to bins.
	By  tone ordering  one can further reduce the bit error rate.

Solution

Solution

(1)  Correct are statements 1 and 3:

• Due to the lack of an interleaver in the fast-path, this path is less protected against bunching errors.
• On the other hand, for AWGN noise, an interleaver does not reduce the bit error rate.
• The disadvantage of an interleaver is the large waiting times (latency), since this distributes the input bits over a large time range in order to turn bundle errors into single errors after the de-interleaver, which is constructed in the same way, and which can then be removed by forward error correction (FEC).

(2)  Correct statements 1, 3, and 4:

• Both the "CRC" (Cyclic Redundancy Check) as well as "Scrambler/De-scrambler" are implemented with shift registers of length $8$ and $23$ respectively.
• The scrambler is redundancy-free (that is, it has exactly as many output bits as input bits) and is self-synchronizing after a short run-in time.
• The redundancy of CRC is very low. It is not error correction in the true sense, but rather control of particularly important data, such as that for frame synchronization.

(3)  Correct statements 2 and 3:

• In the $\rm LNTww$–book "Channel Coding", there is a detailed chapter on the" Reed-Solomon Codes".
• These are byte-level block codes, i.e., not symbol-by-symbol coding.

(4)  Correct are statements 1 and 2 in contrast to the last two:

• The "Interleaving" is redundancy-free and results in large latency and delay, so it should be avoided for real-time applications.

(5)  All of the above statements are correct, as can be read in detail on the "Gain scaling and tone ordering" page.